Character display system

ABSTRACT

Selected characters each identified by a bit code are advanced serially to a memory. The memory is formatted for control of a cathode ray tube display operating to legibly display all characters in the memory. A major raster traces lines of character positions. A minor raster traces each character in a dot matrix at each character position.

United States Patent 1191 Cull et al. Feb. 12, 1974 [5 CHARACTER DISPLAY SYSTEM 3,231,322 10/1966 Evans... 340 324 A 3,426,344 2/l969 Clark 1 v 340/324 A [75] lmemors- Duncan Cull 3,281,831 8/1966 Yanishevsky 340 324 A Culbertson, both of Dayton, 01110 3,500,327 3/1970 BClCllCl' et al 340 324 A [73] Assignee: The NationalCash Register Company, Dayton, Ohio Primary ExaminerJohn W. Caldwell Assistant Examiner-Marshall M. Curtis [22] Flled' June 1971 Attorney, Agent, or FirmJ. T. Cavender; Albert L. [21] Appl. No.: 150,001 7 Sessler, Jr.; Edward Dugas Related US. Application Data [62] Division of Ser. No. 836,270, June 25, 1969, Pat. No. [57] ABSTRACT Selected characters each 1dent1fied by a bit code are 52 us. c1. 340/324 AD 340/168 SR advanced serially a memmy- The memmy is 51 int. c1. G06f 3/14 matted for comm of a cathode ray tube display "Per [58] Field of Search. 340/324 A 168 SR 324 AD ating to legibly display all characters in the memory. A major raster traces lines of character positlons. A [56] References Cited minor raster traces each character in a dot matrix at UNITED STATES PATENTS each character position. 3,423,626 1/1969 Bouchard 340/324 A 5 Claims, 16 Drawing Figures PROM SERIALIZER 318,5 5,

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' sum 11UF12 'FIG. IIB v 255?; 254 l96 249- 25?)l g 4 IN TORS DUNCAN CULL 8n 2.2N E. GUI? SON BY MMiZM THEIR ATTORNEYS CHARACTER DISPLAY SYSTEM This application is a division of US. patent application Ser. No. 836,270, now US. Pat. No. 3,668,661,

filed June 25, 1969, in the names of Duncan E. Cull and Alvin E. Culbertson, Inventors.

The invention herein described was made in the course of or under a contract or'subcontract thereunder, with the Department of the Air Force.

This invention relates to a memory system and associated display circuitry which enables a message to be composed, visually displayed and edited in the memory over a relatively long period of time. However, the invention is' not necessarily so limited.

The present invention has been evolved to meet the needs of a communication system in which a message is composed by introducing coded character information into a memory, inspected by using the coded information in the memory to control a character display such as can be produced with a cathode ray tube, transmitted in composed form by suitable means such as frequency modulated radio frequency signals, and imprinted in decoded character form as transmission occurs to permanently record each message transmitted. A requirement for the system is that the system equipment stand ready at all times to receive information directed. to the system from a remote station. A further requirement of the system is an ability to print out in the form of adecoded permanent record any information which has been received thereby.

An important ingredient for a system having the foregoing capabilities is a memory circuit which enables retention of messages being composed, which enables editing of messages as they are being composed, which enables retrieval of the composed message an indefinite number of times for refreshing a cathode ray tube display andwhich at all times stands prepared to preferentially receive new information or messages from remote stations.

An object of the present invention is to provide improved circuitry for converting the six bit data representing each character to a serial data stream which has its data properly organized for further conversion to a rectangular dot matrix capable of representing the actual character encoded for purposes of display, printout, and the like.

By way of example, the present invention is adapted to convert the six data bits representing a single character to a serialized stream of 35 bits convertible to a X 7 dot matrix.

A still further object of the present invention is to provide a cathode ray tube display unit having a major raster system for locating the positions of characters to be displayed by the cathode ray tube and having a minor raster system for converting serialized bit information to a rectangular dot display at each character position selected by the major raster system.

More particularly, the cathode ray tube display unit of the present invention has among its objects the creation of a major raster which progressively selects 384 character positions organized in 12 lines each comprising 32 character positions, and the display at each character position of a selected character arranged within a 5 X 7 dot matrix or minor raster, the display being cycled indefinitely to continuously refresh the cathode ray tube display.

Other objects and advantages reside in the construction of parts, the combination therof, the method of manufacture, and the mode of operation, as will become more apparent from the following description.

In the drawings:

FIG. 1 is a chart illustrating a six bit code employed in the present invention.

FIG. 2 is a schematic drawing of a keyboard mechanism used in the present invention to produce the appropriate six bit code for each character key depressed on the keyboard.

FIG. 3 isa block diagram illustrating the interrelationship of clock signals employed in the present invention.

FIG. 4 is a schematic illustration of representative gates for decoding the six bit code employed in the present invention.

FIG. 5 is a chart illustrating the relationship between the decode gates of FIG. 4 and the six bit code diagrammed in FIG. 1.

FIG. 6 schematically illustrates circuitry for converting character data decoded with the gates of FIG. 4 to a 35 bit code.

FIG. 7 is a schematic diagram illustrating the-development of the 35 bit code.

FIG. 8 is a schematic diagram of circuitry employed to serialize the foregoing 35 bit code, this figure being split into two parts designated FIG. 8A and FIG. 83.

FIG. 9 is a circuit diagram of the horizontal control for a major display raster, this circuit diagram being split into two parts designated FIG. 9A and FIG. 98.

FIG. 10 is a circuit diagram of a vertical control for the major display raster, this circuit diagram being split into two parts designated FIG. 10A and FIG. 108.

FIG. 11 is a circuit diagram of a minor raster control for tracing 5 X 7 character display matrices at character sites selected by the major raster circuitry, this figure being split into two parts designated FIG. 11A and FIG. 118.

FIG. 12 is a block diagram illustrating the operation of a cathode ray tube display circuit embodying the foregoing major and minor rasters.

To provide a suitable format within which to describe the present invention, FIG. 1 illustrates a representative type of code for character information which is suitable for use in the present invention. The code is conventionally referred to as a 6 bit code. Each bit is a binary bit which can have either a 0 state or a I state. The terminology used herein to describe the possible states of each bit is somewhat arbitrary, since others in the trade may use such terms as true and false or on and off or positive and negative" in reference to the states which each bit in the code can occupy.

An inspection of FIG. 1 will reveal that the six bit code has been organized to allow encoding of various alphabetic and numeric characters and punctuation symbols so as to enable encoding of conventional messages. It can be noted that the six bits 1, 0, 0, 0, 0, O (in order, beginning with the sixth bit) represent a space as might be employed to separate two words. The letter R, for example, is represented by the bits, in order, 0, l, 0, 0, l, 0. In all, the six bit code is organized to represent 60 letters, numbers, punctuation marks, etc., and three control characters.

The three control characters have been enclosed in boxes for easy recognition. One of the control characters is a sinusoidal line enclosed in a box. This character is represented by the bits 0, 1, l, 1, O, 0. As will be more fully explained in a latter part of this description, this control character is a line advance character which causes the message to be continued on a following line" and simulates the function of a carriage return on a typewriter.

A second control character is represented by a caret enclosed in a box and comprises the bits 0, 1, l, 1, l, this control character is introduced into the memory for the purpose of reporting out of the memory the end of a message.

The third control character appears in FIG. 1 as a horizontal line enclosed in a box and is represented by the bits 0, l, l, 1, l, 1. This control character is introduced into the memory to identify and report out the start of a message.

One of the characters which is within a box is a slanted line represented by all bits zero. This control character is a nonfunctional null character which allows the system to have a keyboard arrangement which is of conventional appearance.

The preferred character source for introducing the 60 possible characters and three operative controls into the memory is a keyboard, not shown, resembling a typewriter keyboard. Instead of having keys which operate typewriter key bars, however, a keyboard useful in the present invention utilizes keys which position mirrors to reflect appropriately directed light beams upon photoresistive elements which undergo a marked change in resistance upon exposure to light. Such a keyboard arrangement is shown schematically in FIG. 2.

Thus, FIG. 2 illustrates a keyboard key 1, which represents the character R. Attached to the key 1 is a mirror 2, which can be positioned by depressing the key 1 against a spring load (not shown) to interrupt and reflect a light beam shown schematically at 3. With the key 1 depressed, the light beam is reflected upon a photoresistive element 4 to substantially reduce its resistance to a ground terminal 6. The ground terminal 6 connects through the photoresistive element 4 to an encoder board 5. The board supports six conductive output lines labeled B1, B2, B3, B4, B5, and B6. These output lines deliver the six bits of information which will report that the character R has been depressed on the keyboard and is to be introduced into the memory system.

Referring particularly to the output line B1, this line connects through a conductor 11 and a resistor 8 to a voltage terminal 7. Within the framework of the pres ent disclosure, this voltage terminal is a positive terminal.

The terminal 7 has reference to a ground at 10 through a diode 9, which blocks current flow to ground.

One end of the conductor 11 connects to a terminal 13, which is isolated from ground. The opposite end of the conductor 11 serves as an input to a NAND gate 14 connected as an inverter. The presence of a positive voltage on the line 11 causes the NAND gate 14 to output a low voltage, which is essentially ground, to its output 15. This voltage serves as an input to a second NAND gate 16, which also serves as an inverter, applying a positive voltage to its output at 17.

A separate voltage supply and gate structure which is identical to that described with reference to the bit line B1 is provided for each of the other bit lines B2 through B6. The voltage source and gate structures for the bit lines B2, B3, B4, and B5 have been eliminated to conserve space in the drawings.

It will be noted that the bit lines B1, B3, B4, and B6 are ganged together by the conductor 18. Since these bit lines have no connection to the photo-resistor 4, they will be unaffected by depression of the key 1, and their outputs, as at 15, will remain essentially at ground level irrespective of the position of the key 1.

The bit lines B2 and B5, on the other hand, are connected by the diodes 20 and 21, respectively, to the photo-resistor 4. When the key 1 is depressed, the reflection of light to the photo-resistor 4 substantially reducesthe resistance between ground and the bit lines B2 and B5. As a result, the input to the NAND gates 14 associated with these bit lines will drop essentially to ground, and the outputs from these NAND gateswill shift to a positive voltage. Accordingly, the NAN D gate 14 outputs from the bit lines B1 through B6 will be, in order, 0, l, O, 0, l, 0 when the key 1 is depressed. Reference to FIG. 1 will show that this pattern of output lines represents the code for the character R.

There is one NAND gate 16 for each of the bit lines. When the key 1 is not depressed, all of the NAND gates 16 have a positive voltage or 1 output. These NAND gates are ganged together as a wired OR by means of the conductor 22, which applies the positive voltages of the outputs of the NAND gates 16 to a one-shot 23.

When none of the keyboard keys are depressed, the voltage on the conductor 22 charges a capacitor in the R-C timing circuit, not shown, of the one-shot 23. When the key 1 is depressed, the NAND gates 16 associated with the bit lines B2 and B5 effectively ground the conductor 22. This releases the R-C charging circuit of the one-shot 23, causing the one-shot to generate a timed pulse on the conductor 24.

The pulse generated by the one-shot 23 is used as a strobe to advance the six bit code generated by depression of the character R toward the memory system. For convenience, the strobe will hereinafter be referred to as the strobe K.

It will be noted, of course, that generation of the strobe K by means of the one-shot 23 has not altered the coded information appearing on the outputs 15 of the NAND gates 14. Such information remains constant so long as the key R" is depressed.

While FIG. 2 illustrates only the character key for encoding the letter R," it will be understood that each of the other characters depicted in FIG. 1 has a comparable key, photo-resistor, and encode board for encoding the appropriate code depicted for each character appearing in FIG. 1. Thus, all 0 bit lines for each code are produced by isolating the bit lines as at the terminal 13, and all 1 bit lines that may be required are produced by connecting the bit lines to the photo-resistor for the particular character key that will be depressed.

Regardless of the key depressed, except the null key, it is desired that the strobe K be fired, and this requires that, for each key, at least one of the bits produced thereby shift to a I when the key is depressed, thus allowing a NAND gate comparable to the gate 16 to effectively ground the line 22 and thereby trigger the one-shot 23. Since the null key previously described produces a code comprising all Os, the stobe K is not generated when the null key is depressed. As will appear more fully in the following, the strobe K is required to advance information generated by operation of the key toward the memory, and, accordingly, depression of the null key, which fails to generate a stobe, has no influence on the memory.

In order to advance the coded information produced at the keyboard into the memory system of the present invention, a series of clock frequencies and associated logic circuitry regulated by means of the clock frequencies is provided. All clock signals used in the present apparatus are derived from a crystal controlled oscillator in a manner schematically represented in FIG. 3. The signal from the crystal controlled oscillator, which is desirably in the megacycle range, is first divided by three through a divide-by-three counter to produce a clock identified by the reference character C1. This clock C1 is divided by ten through a five flip-flop counter designated the A counter to produce a clock designated C2. This clock C2 is in turn divided by six through a three flip-flop counter designated the B counter to produce a clockdesignated C3.

The clock C3 is again divided by thirty-six through a six flip-flop counter designated the D counter to produce a clock designated C4. The clock C4 is further divided by twelve through a four flip-flop counter designated the E counter to produce a clock designated C6.

As noted, the D counter is a six flip-flop counter. By means ofa gate G10, the D counter is caused to output a clock C5, which can be represented in Boolean algebra as D6 (D1 D2) (C3). As understood by those skilled in the art, this expression tells that the state of the flip-flop representing the sixth stage of the D counter is ANDed with the state of the first stage flipflop or the state of the second stage flip-flop, inverted, and the resultant signal ANDed with the clock C3 to produce the new clock C5. The clock C5 is essentially the clock C3, but, during the time the clock C3 provides 36 pulses, the clock C5 will duplicate the clock C3 for 33 pulses, then skip three pulses. In practical effect, the clock C5 is an adjustment of the clock C3 to provide a clock which exactly conforms to the memory capacity, as will be more fully explained in succeeding remarks.

Throughout the following specification, various clock characteristics derived from the counters illustrated in FIG. 3 will be expressed in Boolean language. Whenever the Boolean expression for a clock characteristic includes a counter state, the state will be identified by an asterisk The D counter, for example, has six flip-flops connected to count through 36 states. The expression Do* refers to the first count level of the D counter. The expression D35* refers to the 36th state. Whenever the Boolean expression for a clock characteristic includes the state of a particular flip-flop in a particular counter, the flip-flop is designated by the letter which identifies the counter in which the flip-flop appears and a suffix identifying the position of the flipflop in the counter. Thus, D1 expresses that the first flip-flop in the D counter is in its 1 state. Di correspondingly designates that the first flip-flop in the D counter is in its 0 state.

For the purpose of illustrating the present invention, the memory system will be described as one capable of storing 396 characters. As discussed previously, each character is coded in the form of six bits. To enable storage of all six bits representing each character, the memory is constructed with six shift registers each capable of shifting through 395 states. The six shift registers are shifted in parallel by the clock C5, and, for convenience hereinafter, each shift register state may sometimes be referred to as a memory cell.

The memory and other associated circuitry such as memory buffers keyboard buffers and the like are disclosed in detail in US. Pat. application Ser. No. 836,270 of which this application is a division. For purposes'of this invention it is only necessary that the memory have a plurality of character code memory cells and that the codes be clocked through the memory cells.

The character information stored in the memory is used to continuously refresh a cathode ray tube display. The cathode ray tube display unit is designed to display six lines each comprising 32 characters of information received from the keyboard and an additional six lines each comprising 32 characters of information that may be externally received from another source. For the purpose of properly formatting the cathode ray tube display, each line of 32 characters is followed by 33rd character, designated the line advance character. One function of the line advance character, is to set aside time for the cathode ray tube display unit to retrace in preparation for the display of succeeding characters in the memory on a next lower line of the cathode ray tube display. The cathode mechanism permits the operator to visually examine the message as it is being composed and to visually review the message after it has been fully composed. To simplify the description of the CRT mechanism, a fully composed message will be assumed.

The operating concept of the CRT display mechanism is as follows. By means of the D counter, a cathode ray beam is caused to progress in coarse increments through 32 horizontally-spaced character positions on a cathode ray screen. The beam is then dropped downwardly on the screen a distance corresponding to the desired spacing between lines of the display and advanced horizontally through 32 more character positions, and this display process is repeated to cause the cathode ray beam to coarsely trace out 12 horizontal lines each having 32 character positions therein. Six of these horizontal lines are reserved for a display of composed messages, and the other six are reserved for display of messages that will be received in a manner yet to be described.

As the cathode ray beam is coarsely moved to each of its 384 character positions (12 lines each having 32 characters), clock signals received from the A and B counters are employed to advance the beam at each character position through a six-line by lO-line rectangular matrix. By means of blanking signals applied to the cathode ray tube cathode, luminous dots are permitted to form only at discrete points in a five-by-seven portion of the matrix traced out at each character position. A legible luminous character is thus traced out at each of the 384 character positions reached by the cathode ray beam.

For convenience, the coarse movement of the cathode ray beam through 384 character positions is hereinafter referred to as a major raster. The fine or vernier movement of the cathode ray beam through a six-by-IO rectangular matrix at each coarse position established by the major raster is referred to as a minor raster.

While the minor raster provides a five-by-seven matrix of dots representing any given character, this matrix will be generated within an essentially six-by-lO matrix area. The remaining portions of the six-by-lO matrix area are 'used to provide spacesbetween the characters and spaces between the lines. The five-byseven-dot matrix which is reserved for a display of characters at each character position is controlled by a 35-bit character code supplied serially to an amplifier which blanks the filament. It is therefore necessary to convert the six-bit character codes stored in the memory to 35-bit character codes which can be applied serially to the blanking amplifier. In ensuing paragraphs, the six-bit to 35-bit character code conversion will be described.

Sixty-four recognition gates are provided each capable of recognizing one of the 64 possible characters that can reside in the memory. Three such gates are illustrated in FIG. 4 and are identified by the reference characters G87, G88, and G89.

The gate G87 is a NAND gate connected to recognize only the six bit code for the letter Q. It will recognize no other code. Thus, the bits for the letter O are l, 0, 0, 0, 1, 0. For the purpose of recognizing the letter O, the NAND gate G87 inputs are, respectively, Bl, E, E, B1, B5, and B6, as received from the memory buffer details of the memory buffer are covered in U.S. Pat. application Ser. No. 836,270. Whenever the character Q" is in the memory buffer, all inputs to the gate G87 will be I, and, accordingly, the gate G86 will be forced to output a 0. This is inverted through a conventional inverter, so that an output of 1 appears on the line marked Q in FIG. 4. This 0" line will be a 1 only when the six bit code for the character Q" resides in the memo ry.

FIG. tabulates the Q and Q values that will be received from the memory buffer when any one of the Q, R, and S characters is lodged in the memory buffer. By comparison of the inputs to the gate G88 with the Q and 6 values from the memory buffer tabulated in FIG. 5, it can be seen that the gate G88 is conditioned to recognize only the character R. Likewise, the gate G89 is conditioned to recognize only the character S."

It will be readily understood that FIGS. 4 and 5 are merely illustrative of the technique employed to develop character recognition gates. In fact, only 63 recognition gates are required. Thus, the previously discussed null character is an essentially inoperative character, and there is no need to recognize this character.

It is frequently convenient to refer to each of the output lines of the character recognition gates as bit lines. Each of the bit lines from the character recognition gates is connected to a network of diode boards which re-express the characeter being recognized in a 35 bit code. FIG. 6 illustrates seven diode boards, labeled X1, X2, X3, X4, X5, X6, and X7 assembled to produce the thirty-five bit code for the characters 0, P, Q, R", S", and T.

These diode boards are of a commercially available type in which an array of diodes is connected by fusible links between horizontal conductors insulated from vertical conductors. To conform the diode boards to the desired code, the fusible links are ruptured, or blown out, as desired. FIG. 6 illustrates only those diodes which remain in the circuitry after the fusible links have been ruptured. It will be noted that initially all horizontal conductors were brought out to terminals on the left sides of the diode boards. To simplify the drawing, those horizontal lines that have been removed from the circuitry by rupture of the fusible links have been omitted, but, for convenience in description, the output terminals for such lines remain in the drawing.

Assuming that the character R" has been recognized in the memory buffer, a voltage level of I will appear at the terminal R illustrated in FIG. 6. By reason of the diode connections illustrated, horizontal conductors 7-1 and 7-5 will all rise to the 1 level when the character R is recognized. The horizontal conductor 7-5 on the board X7 will remain at the 0 level.

On the diode board X6, the output terminals 6-1 and 6-4 will go to a I level, and all other output terminals from the diode board X6 will remain at 0.

It can be noted that the seven diode boards X1 through X7 collectively provide 35 outlet terminals, each capable of having a voltage level of l or 0. When the character R is recognized, a unique portion of the 35 outlet terminals will have a level of 1, and the remainder a level of 0, thus providing a unique 35 bit code for the character R.

FIG. 6 indicates the unique codes for the characters 0, P, Q, R, S, and T. Other networks of diode boards, each comprising seven boards, are used to develop unique 35 bit codes for each character available to the memory.

FIG. 7 illustrates the manner in which the diode boards have been organized. Thus, FIG. 7 shows a matrix comprising five vertical lines and seven horizontal lines. Each of the diode boards X1 through X7 represents a horizontal display line. The five outputs from each diode board in FIG. 6 provide column information for the matrix of FIG. 7. This enables the outputs from the diode boards to be numbered in reference to the matrix position illustrated in FIG. 7. Thus, outlet 7-1 of the diode board X1 can be considered as representing row 1, column 5 of the matrix illustrated in FIG. 7. The terminal designations in FIG. 6 thus depict the rows and columns in which information should be displayed as in FIG. 7. If a dot is placed in FIG. 7 at each point in the matrix where a l is output from the diode boards X1 through X7 when the character R is recognized, as has been done in FIG. 7, the character R appears in the matrix. Each of the 63 character codes available to the memory is thus converted to a 35 bit code in the fashion described to provide a visually recognizable character.

For purposes of the CRT display, it is required that the 35 bit codes, one for each character, be converted to a 35 bit serialized stream of binary data. This is accomplished with the aid of the A and B clock counters (FIG. 3) and the circuit illustrated in FIG. 8.

The A counter is assembled as a divide-by-IO shift counter. For convenience, the 10 states to which the A counter shifts are designated A0* A1* A2* A3* A4* A5* A6* A7* A8* and A9*. The B counter is a divideby-six shift counter, and the six states of the B counter are designated B0* Bl* B2* B3* B4* and B5*.

By means of conventional gating, not shown, the A3* through A9* A counter states are applied to the terminals 81 through 87, respectively, in FIG. 8. The Bl* through B5* states of the B counter are applied to the terminals 88 through 92, respectively, in FIG. 8. It will be recognized by those skilled in the art that, when the B counter is in the Bl* state, the A counter will shift through all 10 of its states, and, when the B counter is in its 82* state, the A counter will again shift through all 10 of its states, and so on for each state of the B counter.

Assume, for example, that the character R has been detected in the memory buffer by its recognition gate G88, and, perforce, the appropriate outputs of the recognized in the memory buffer, the appropriate terminals in FIG. 8 will carry ls or Os as determined by the diode boards in FIG. 6.

During the time the character R remains in the memory buffer, the B clock will progress through all six of its states one time, and the A clock will progress through all 10 of its states six times, this being a necessary result of the fact that the characters are clocked through the memory buffer by the CS clock.

It can be seen that the circuitry of FIG. 8 has a single outlet at the terminal 93. It also'has a clock input to be described later at the terminal 94.

Assuming that the character R has just been recognized and the B counter is in its Bl* state, the A counter will shift progressively through its ten states, A* A9* For the first three states of the A counter, A0* A2*, both inputs to a NAND gate G92 will be 0s, and this NAND gate will output a steady 1. When the A counter reaches its A3* state, the terminal 81 will go to a l voltage. Reference to FIG. 6 shows that output 7-1 from the diode boards is also at a l voltage. These 1 voltages will be ANDed during the time of the A3* state through the gate G90 to place a l on one of the five inputs to the NOR gate G91. All other inputs to the gate G91'are Os, since the A counter is in the A3* state. The NOR gate G91 accordingly outputs a O to the NAND gate G92, which, being disabled, outputs a l to the NAND gate G94. This 1 is inverted by the gate G94 so as to disable the gate G95, causing this gate to output a 1.

From the foregoing description respecting FIG. 1, it can be recognized that the A counter will progress from its state A3* up to its state A9*, sampling the diode board outputs for the seven rows of column one in the matrix of FIG. 7. It will be noted that the sampling proceeds upwardly from row seven to row one during Bl* time. The coincidence gating illustrated in FIG. 8 will cause the gate G95 to output a l at each rowwhere the diode boards output a l and to output a O at each row where the diode boards output a 0. With reference to the letter R" for example, the diode boards output a l for each row in column one of the display (FIG. 7), and, accordingly, the NAND gate G95 will output seven regularly-spaced ls to its terminal 93.

During 82* time, the circuitry of FIG. 8 will repeat the sampling process, but this time the sampling will proceed upwardly along column two of the display matrix (FIG. 7). Accordingly, the NAND gate G95 will output 0, 0 0,1, 0, 0,1.

From the foregoing description, it is evident that during B3* time the third column of the display matrix will be sampled, during B4* time the fourth column sampled, and during 35* time the fifth column sampled. Since any given character remains in the memory buffer for a time equal substantially to the time separation between two successive C clock pulses, there is intrinsically ample time for completion of the foregoing sampling process. It will be noted that the sampling process carries the A counter six times through its ten states. During B0* time, the NAND gate G95 has all inputs 1 and thus outputs a steady 0. As will appear more fully when the CRT raster circuitry is discussed, the resulting empty column immediately to the left of each character display is used to assure adequate character spacing.

By the same reasoning, the gate G outputs a O at A0* time, A1* time, and A2* time, and this circuit characteristic is used to assure adequate spacing between lines of the display.

It is believed evident from the foregoing description that the result of the sampling process is a serialized bit stream at the terminal 93 in FIG. 8 which comprises 60 bits spaced by the time interval between A counter states. Many of the bits in this stream will always be a O for the reasons described. Ones" will appear in this 60 bit stream at only those sites where illumination will be desired on the CRT screen, and, basically, the places where a 1 can appear in the 60 bit stream of data resulting from each sampling sequence are confined to the seven row and five column matrix used for character representation.

It was noted at the beginning of this specification that the keyboard includes a space key (bits 0, 0, 0, 0, 0, l) which is actually placed in the memory, and thus it is not a null character. It will be understood, however, that the diode boards responsive to this space character are designed to provide no illumination in the space area. It is also possible for the memory to contain null characters resulting from a line advance characters having been entered into the memory from the keyboard. Such null characters also will give rise to no CRT image.

Since it is possible for relatively large areas of the CRT display to contain no image, it is found desirable to nevertheless image each character position in the array so that the keyboard operator will-not be confused as to the formatting of the CRT display. This is accomplished in the present invention by gating the A2* B3* clock counter state to the terminal 94 in FIG. 8. This signal is passed by an AND gate G96 in FIG. 8, and, as a result, each 60 bit serialized stream resulting from the sampling by the A and B counters in the manner previously described will contain a l in the third column of the display area (FIG. 7) and immediately below the first row of the display area. This 1 is used to always generate a luminous dot in the third column and below each character display area of the CRT, thus informing the keyboard operator of the available display area and the available character sites.

In the following paragraphs it will be described how this 60 bit serialized stream derived from the sampling operation provided by the circuitry of FIG. 8 is used to produce character displays on the screen of the cathode ray tube.

The CRT display circuitry is outlined in block diagram form in FIG. 12. As conventional, the cathode ray tube is energized through a high voltage delay circuit, auto transformer and a high voltage power supply. Energized by the high voltage input is a D. C. supply which supplies energy to a focus control through a focus supply circuit. Filament current for the cathode ray tube is supplied through a filament transformer. The foregoing elements are conventional to any cathode ray tube apparatus and require no further explanation, although it may be noted that the high voltage delay circuit is employed in the present cathode ray tube apparatus to delay energization of the cathode ray tube until the various display controls to be described have become operative.

As frequently conventional, the cathode ray tube includes a main yoke and a minor yoke, which are used to direct the cathode ray beam to selected areas of a cathode ray screen. The beam is caused to progress horizontally across the screen in synchronized relationship to the D counter (FIG. 3) by converting selected digital clock signals from the D counter to analog voltage signals in a main horizontal digital to analog converter. The output of this converter is amplified in a main horizontal deflection amplifier, which, by controlling the current in the main yoke, causes the cathode ray beam to advance from left to right on the screen, as observed'by one viewing the screen.

Selected clock signals derived from the D and E counters are converted to analog voltages in a main vertical digital to analog converter, amplified in a main vertical deflection amplifier, and applied to the main yoke to control the vertical elevation at which the beam progresses horizontally across the screen. The clock signals are so utilized that the cathode ray beam will progress from left to right across the screen 12 times at 12 different vertical levels as if to write 12 lines of information on the screen.

Each horizontal sweep of the cathode ray beam across the screen proceeds in a stepwise fashion, so that the beam stops momentarily at 32 equally-spaced positions across the screen. Each of these 32 positions represents a position at which a character can be displayed. The character display proceeds under control of the A and B counters. Selected signals derived from the B counter are applied to a minor horizontal digital to analog converter, which outputs to a minor horizontal deflection amplifier driving the minor yoke to cause the cathode ray beam to shift horizontally in vernier increments to five horizontally spaced positions. As these horizontal shifts occur, a selected signal from the A counter controls the operation of a minor vertical deflection amplifier, which drives the minor yoke to cause the cathode ray beam to sweep upwardly and return it at each horizontally spaced position established by the minor horizontal deflection system.

It will be understood that the minor horizontal and vertical deflections occur very quickly at each of the 32 character positions reached by the cathode ray beam in each of its horizontal sweeps across the cathode ray screen. As will be more fully explained later in this description, the vertical sweep of the cathode ray beam produced by the minor vertical deflection amplifier can be considered as a sweep through seven vertically spaced positions. Thus, at each of the 32 character positions reached by the cathode ray beam in each of its horizontal sweeps across the screen, a five-by-seven character matrix is traced.

Associated with the cathode ray tube are a blanking amplifier and a power supply therefor. The blanking amplifier normally biases the grid of the cathode ray tube so as to cut off the cathode ray beam during each time the minor yoke is modulated so as to trace out the aforementioned five-by-seven matrix, the serialized 60 bit stream produced by the serializer circuitry of FIG. 8 is applied to the blanking amplifier. At each position along the stream where a 1 appears, the blanking amplifier is disabled so as to enable the cathode ray beam to strike the cathode ray screen. The serialized bit stream is thus a stream of blanking control bits.

As previously noted, a 1 will always appear at the base of the third column in each five-by-seven character matrix. Thus, the cathode ray beam will be unblanked at least once for each character position. Additional unblanking can occur only in a five-by-seven display area.

It will be recalled that the memory includes 396 memory cells. As previously discussed, these 396 cells are divided, in effect, into 12 lines each comprising 33 characters, the 33rd character in each line being a line advance character which is not displayed on the cathode ray tube. The cathode ray tube display system is thus designed to display 12 lines, each comprising 32 characters. As will be subsequently explained in greater detail, each line of the display area is adapted to display 32 characters derived from the memory, and, as the cathode ray beam is directed through its 12 horizontal lines of display, all characters with the exception of line advance characters residing in the memory will be displayed. Thus, the display circuitry of the present invention is intended to display the entire memory at one time. Recalling also that the memory is continuously cycled through the memory buffer, it will be understood that this continuous cycling of the memory is used to continuously refresh the cathode ray tube display, so that all characters present in the memory, with the exception of line advance characters, are continuously visible on the cathode ray beam screen.

It is convenient to consider the cathode ray tube as executing two relatively independent rasters. The first raster, herein called a major raster, comprises the left to right horizontal movements of the cathode ray tube through 12 vertically spaced horizontal lines. The second raster, herein called the minor raster, comprises the six-by-lO character matrix which traces out a character at each of the 32 positions established by the major raster in each of the 12 lines of the display.

The beam control means for producing the left to right horizontal movements of the major raster is dis played primarily in FIG. 9. The clocks for the circuit are developed as follows.

The output of the D1 flip-flop in the D clock counter is applied to the terminal 124 in FIG. 11. The output of the D6 flip-flop in the D clock counter is applied to the terminal 126 in FIG. 11. The D6 flip-flop output is inverted to I)? by the gate G112 and NANDed with D1 in the gate G113, and the re s u lt is inverted in the gate G1 14 to produce an output D6 D1 at the terminal 127 in FIG. 11. This signal appears at the terminal 127 in FIG. 9 and serves as one of the clocks for the major horizontal raster.

In like fashion, Dz from the gate G112 is NANDed with D2 in the gate G115 of FIG. 11, and the result is inverted through the gate G116 to produce the clock signal 56 D2 at the terminal 128 in FIG. 1 1. The terminal 128 re-appears in FIG. 9 to supply the clock signal D 6 D2 to the major horizontal raster circuitry.

Clock signals D3, D4, and D5 are applied directly from the D counter to the terminals 129, 130, and 131 of FIG. 9. A sixth clock signal for controlling the major horizontal raster is derived from the circuitry of FIGS. 10 and 11. Referring to FIG. 20, the output of the flipfiop D1 in the D counter brought to the terminal 124 is inverted in the gate G127 to bring D1 to the terminal 120. This terminal re-appears in FIG. 10, where 51 is used as one input to a NAND gate G110. In like fashion, the output of the flip-flop D2 in the D counter brought to the terminal 125 of FIG. 11 is inverted in gate G128, so as to apply D2 to the terminal 121 in FIG. 11. This terminal re-appears in FIG. 10, where it serves as the second input to the gate G110. A third input to the gate G110 in FIG. is the output of the flip-flop D6 in the D clock counter which is brought to the terminal 122 in FIG. 10. The resulting output of the NAND gate G110 is inverted in the gate G111, where the signal D 1 D2 D6 is applied to the terminal 123. The terminal 123 re-appears in FIG. 9 as the sixth clock signal for the major horizontal raster circuitry.

The foregoing six clock inputs to FIG. 9 are separately applied to transistor triplets designated 135, 136, 137, 138, 139, and 140. The triplet 135, for example, comprises transistors Q1, Q2, and Q3. The triplets are all supplied with a positive reference voltage at the terminal 132 and a ground at the terminal 133. With reference to the triplet 135, those skilled in the art will recognize that the transistors Q1 and Q3 are normally nonconductive and the transistor O2 is conductive until a l voltage reaches the terminal 127, whereupon the transistors Q1 and Q3 become conductive, while Q2 goes off. When O2 is conductive, the voltage on a conductor 135a is essentially ground. When 02 goes off, the voltage on the conductor 135a rises to the positive reference voltage. The transistor triplet 135 thus behaves as a switch, switching the conductor 135a to the reference voltage when a clock pulse arrives at the terminal 127 and to ground when a clock pulse is not present on the terminal 127. The transistor triplets 136, 137, 138, 139, and 140 act in the identical fashion, each being controlled by the particular clock input thereto.

The foregoing transistor triplets control the voltage inputs to an R-2R binary weighted resistance ladder grounded at the terminal 134 and including the resistances 141, 142, 143, 144, 145, and 146.

Assuming that the D counter is initially in a 0 state, wherein all of its flip-flops are outputting Os, the operation proceeds as follows. Each of the resistances 141 through 146 in the resistance ladder is grounded at one end. When a first clock signal 1Y5 D1 is received at the terminal 127, O2 goes off and Q1 goes on, so that a small portion of the positive reference voltage appears on a conductor 147. This condition occurs when the flip-flop D1 in the D counter first reaches its 1 state.

The flip-flop D1 then shifts to 0 as D2 shifts to its 1 state, thus switching the positive reference voltage from the resistance 141 to the resistance 142. The conductor 147 now receives a higher voltage through the resistance 142. The circuit is so balanced that the voltage on the conductor 147 is now just twice the voltage that appeared when only the transistor triplet 135 was conducting.

In the next stage of the D counter, both the flip-flops D1 and D2 are in their 1 state, and accordingly both the triplets 135 and 136 are conducting. The voltage on the conductor 147 is then three times the voltage that appeared when only the flip-flop D1 was in its I state. A pattern can now be recognized in which, a the D counter counts upwardly from a first count (D6 D1), the voltage on the conductor 147 increases by equal increments, the voltage always being a multiple of the voltage which appeared on the conductor 147 at the fi rst count level. It will be recognized, of course, that D1 D2 D6 represents a count up to 32 in the D counter and represents the highest count recognized by the circuitry of FIG. 9. Thus, the D counter count levels 33, 34, 35, and 36 do not influence the circuitry of FIG. 9, which reacts only to the first 32 count levels of the D counter. As the D counter progresses through the first thirty-two counts thereof, the voltage on the conductor 147 progresses upwardly in 32 equal increments. Thus, the circuitry of FIG. 9 has succeeded in converting the first 32 digital count signals from the D counter to voltage analogs.

As appears in FIG. 9, the voltage from the conductor 147 is applied to an amplifier 148, and the output of the amplifier 148 to a second amplifier 149. The second amplifier acts as a voltage-to-current converter. The biasing circuitry for these amplifiers is conventional and therefore not described in detail, it being sufficient to note that positive voltage is supplied on the conductor 151 from the terminal 132 and a ground supplied on the conductor 152 from the terminal 133. A separate positive voltage supply is brought in at the terminal 153, and a separate negative voltage supply is brought in at the terminal 154. The output of the amplifier 149 to the terminal serves as a pre-amplifier to drive a deflection power amplifier, not shown, which is connected through a current-sampling resistor, not shown, to the main horizontal yoke winding. Feedback from the sampling resistor to the terminal 155 is employed to stabilize the amplifier output.

From the foregoing description, it can be recognized that, as the D counter progresses from its basic one count to a count of 32, the cathode ray beam is stepped incrementally across the cathode ray screen in 32 essentially equal steps. The D counter will count on out to 36, and the last four counts of the D counter afford time for the deflection system to recover and return the cathode ray beam from its extreme right deflection to its extreme left deflection.

It was previously described that the major raster travels horizontally through 12 vertically-spaced lines on the CRT screen. The vertical spacing is obtained by means of the beam control circuitry illustrated in FIG. 10. It will be recognized, of course, that a change in the vertical elevation at which the horizontal sweeps of the major raster occur is desired only after the D counter has completed its thirty-second count, so as to complete a horizontal sweep of the major raster. The circuitry of FIG. 10 is thus clocked by the D counter flipflop condition 1T1 D 2 D6 applied to the conductor 156. This clock identifies the end of each horizontal sweep from the circuitry of FIG. 9.

To cause a vertical sweep through twelve vertically spaced positions, the circuitry of FIG. 10 is equipped with a counter mechanism comprising flip-flops V1, V2, V3, and V4. The Q outputs of these four flip-flops are applied by means of conductors 172, 173, 174, and 175, respectively, to transistor triplets 164, 165, 166, and 167. As before, the triplets 164 through 167 are connected between a positive reference voltage at the terminal 161 and ground at the terminal 162. As before, the transistor triplets are used to switch resis' tances 168, 169, 170, and 171, respectively, between ground and the reference voltage. The resistances 168 through 171 are part of a resistance ladder grounded at 163. The output of the resistance ladder appears on the conductor 176.

A reset circuit for the flip-flops V1 through V4 is operated by a four-inputEAND gate G117. The inputs to this NAND gate are E2 (the zero state of the second 

1. In combination, a cathode ray display device and a cyclic memory device storing codes of characters to be displayed by said display device, said display device incluDing means producing a cathode ray beam and a screen adapted to be activated by said beam, beam control means to direct said beam to selected areas of said screen, timing means including a first clock means acting upon said control means to direct said beam across said screen to a plurality of different character display sites, said cyclic memory device having a plurality of code memory cells, said first clock means clocking said codes through said memory cells, said timing means including second clock means acting upon said beam control means to direct said beam through a horizontal and vertical raster pattern at each of said character display sites, means for blanking said cathode ray beam, and display control means responsive to said character codes for providing a serialized stream of blanking control bits proportional to the stored codes to said blanking means and cooperating with said second clock means to disable said blanking means at selected positions in said vertical raster pattern so as to form a dot at each selected position.
 2. The combination of claim 1 wherein said first clock means includes a first clock and said beam control means includes a first digital to analog converter responsive to said first clock to direct said beam horizontally across said screen, said first clock clocking said codes through said memory cells.
 3. The combination of claim 1 in which said serialized stream of blanking control bits comprises groups of bits there being one group of control bits for each horizontally spaced increment in said raster, the control bits in each of said groups controlling the unblanking of said beam during one vertical sweep of said beam.
 4. The combination according to claim 1 wherein said code recognition means comprises a plurality of code recognition gates there being one code recognition gate for each code available to the cyclic memory device, said code recognition means including a plurality of code conversion networks cooperating with said code recognition gates to convert each code recognized to a plurality of groups of binary bits, a plurality of first coincidence gates, there being one coincidence gate for each of said binary bits, means applying states of said fourth clock to said first coincidence gates, a plurality of second coincidence gates, there being one second coincidence gate for each of said groups of bits, means applying states of said third clock to said second coincidence gates, and gate means having a single output combining the outputs of said second coincidence gates.
 5. In combination, a cathode ray display device and a cyclic memory device storing codes of characters to be displayed by said display device, said display device including means producing a cathode ray beam and a screen adapted to be activated by said beam, beam control means to direct said beam to selected areas of said screen, timing means including a first clock means acting upon said control means to direct said beam to a plurality of different character display sites, said cyclic memory device having a plurality of code memory cells, said first clock means clocking said codes through said memory cells, said timing means including second clock means acting on said beam control means to direct said beam through a raster pattern at each of said display sites, said second clock means having different states for different positions of said beam in said raster pattern, said cyclic memory device including a buffer cell, said first clock means advancing a new code to said buffer cell at each of said display sites, blanking means to blank said cathode ray beam, code recognition means responsive to each code residing in said buffer cell cooperating with said second clock means to provide a serialized stream of blanking control bits, there being one blanking control bit for each of said different states of said second clock means, said stream of control bits disabling said blanking means in accordance with the states of the control bits therein as said seconD clock means directs said beam through said raster. 